1. Field of the Invention
The present invention relates to a system and a method for signal transmission, and more particularly, to a system and a method for generating and transmitting encoded DC-balanced data so that DC-balanced data and DC-balanced synchronization codes (DSYNC) are not the same following transmission via a communication link (hereinafter referred to as “channel”).
2. Description of the Related Art
Modern LCD monitors employ an interface that transmits data using optical fiber in order to reduce EMI (electromagnetic interference) and transmission line noise caused by transmission cables.
DC balance is needed in a data transmission system which utilizes optical fiber. Thus, an interface that adopts optical fiber uses a signal transmission approach that achieves transmission of a DC-balanced signal. As is well known in the relevant industry, DC balance is a balance between a ‘High’ logic value and a ‘Low’ logic value of each data bit of a digital data transmission.
FIG. 1 is a high-level block diagram of a conventional signal transmission system that uses 5 channels. The signal transmission system 10 shown in FIG. 1 uses a signal transmission approach (hereinafter referred to as 8B/9B) which encodes 8 bits into 9 bits, and includes a controller 2, a transmitter 4, a receiver 6, an LCD panel 8 and five channels 1, 3, 5, 7 and 9. FIG. 2 is a timing diagram of output signals of a typical video controller.
As shown in FIGS. 1 and 2, the controller 2 outputs a red video signal (R[7:0]), a green video signal (G[7:0]), a blue video signal (B[7:0]), a horizontal synchronization signal (HSYNC), a vertical synchronization signal (VSYNC), a data enable signal (DE) and a clock signal (CLK) to the transmitter 4. Each of the red, green and blue video signals (R[7:0], G[7:0] and B[7:0]) includes 8-bit data.
FIG. 3 shows output signals of the transmitter of FIG. 1. As shown in FIGS. 1 and 3, the transmitter 4 transmits DC-balanced data (DCBR, DCBG, DCBB and SYNC) over four channels 1, 3, 5 and 7 to the receiver 6. The transmitter 4 sends the CLK over channel 9 to the receiver 6.
Here, the DC-balanced data (DCBR, DCBG and DCBB) indicates the encoded video signals (R[7:0], G[7:0] and B[7:0]) respectively and DC-balanced synchronization signal SYNC indicates the encoded 8-bit synchronization signal. The 8-bit synchronization signal is generated according to the logic values of both HSYNC and VSYNC. The DC-balanced data (BCBR, DCBG and DCBB) and SYNC are serialized and output to the receiver 6.
In response to the DC-balanced data (DCBR, DCBG and DCBB), SYNC and CLK, the receiver 6 demodulates the red, green and blue video signals (R[7:0], G[7:0] and B[7:0]), HSYNC, VSYNC and DE. Then, the receiver 6 outputs the demodulated signals to the LCD panel 8.
The LCD panel 8 receives the red, green and blue video signals (R[7:0], G[7:0] and B[7:0]), HSYNC, VSYNC, DE and CLK, and then displays video signals.
Since the conventional data transmission system (10) cannot combine the DC-balanced data (DCBR, DCBG and DCBB) and SYNC, it uses channels 1, 3 and 5 to transmit the DC-balanced data (DCBR, DCBG and DCBB) and channel 7 to transmit the SYNC signal.
The data rate (or data transfer rate) of the conventional data transmission system 10 is determined by the number of data transmission channels (excluding the channel that transmits CLK)×bit stream×operation frequency (MHz).
Therefore, the data rate of the Super Extended Graphic Array (SXGA) that runs at 112 MHz is about 4 Gbps (4×9×112 (MHz)). The high data rate is a disadvantage of the existing signal transmission system 10 which uses 4 channels (excluding the channel that transmits CLK).